1. Field of the Invention
This invention, in several embodiments, relates generally to masking techniques for semiconductor fabrication and, more particularly, to masking techniques including pitch multiplication.
2. Description of the Related Art
As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction.
The trend of decreasing feature size is evident in the integrated circuit (IC) industry, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memories, static random access memories (SRAMs) and ferroelectric (FE) memories. Other examples of integrated circuit memories include MRAM (including magneto resistive elements), programmable fuse memories, programmable conductor memories (including metal-doped chalcogenide glass elements), SRAM, SDRAM, EEPROM and other volatile and non-volatile memory schemes. To take one example, a DRAM conventionally comprises millions of identical circuit elements, known as memory cells. DRAM memory cells conventionally include two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. By decreasing the sizes of the electrical devices that comprise memory cells and the sizes of the conducting lines that access the memory cells, memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells within a given area in memory devices.
Features, such as conductive lines, are conventionally formed using a process in which a pattern defining the features is first formed in a temporary layer over a semiconductor substrate and subsequently transferred to the substrate using conventional etching chemistries. Photolithography is commonly used to pattern such features within a photodefinable (or photoresist) layer. In photolithography, a pattern of features is formed in the photodefinable layer using a process which includes directing light (or radiation) through a reticle having a pattern corresponding to the pattern of features to be formed in the substrate.
The sizes of features can be described by the concept of “pitch,” which is defined as the distance between identical points in two neighboring features. These features are typically defined by spaces between adjacent features. Spaces are typically filled by a material, such as an insulator. As a result, for regular patterns (e.g., in arrays), pitch can be viewed as the sum of the width of a feature and the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light (or radiation) wavelength, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Consequently, the minimum pitch restriction of a given photolithographic technique is an impediment to further reduction in feature sizes.
“Pitch multiplication” or “pitch doubling” is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in FIGS. 1A-1F and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, a pattern of lines 10 is photolithographically formed in a photoresist layer, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30. As shown in FIG. 1B, the pattern is then transferred using an etch (such as an anisotropic etch) to the layer 20, thereby forming placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in FIG. 1F. Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.
While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. Pitch can thus be used in two converse senses: the distance between identical elements in a regular pattern and the number of features in a fixed linear distance. Pitch multiplication (or pitch doubling) assumes the latter sense, i.e., if the pitch is doubled, two features and spaces are defined in a region where photolithography had defined only one feature and space.
U.S. patent application Ser. No. 11/150,408, to Wells (“Wells”), filed Jun. 9, 2005, discloses methods for forming pitch-multiplied features using spacers as mandrels for subsequent spacers. According to methods disclosed therein, a first set of spacers is formed on sidewalls of mandrels over a substrate. The width of the spacers is selected based upon the sidewall positions so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers and etched back to form a second set of spacers. The widths of the second set of spacers are chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set of spacers is used as a mask for etching a substrate. Accordingly, pitch multiplication by a factor of four is achieved, and this technique can therefore be extended to pitch multiplication by a factor of 8, 16, etc.
As another example, U.S. patent application Ser. No. 11/144,543 to Sant et al. (“Sant”), filed Jun. 2, 2005, discloses methods for forming pitch-multiplied features using multiple stages of spacer formation. According to methods disclosed therein, multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. As an alternative, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern.
Methods using multiple spacer formation steps for pitch multiplication lead to large processing costs. For example, the process of U.S. patent application Ser. No. 11/150,408 of Wells forms spacers twice to achieve pitch multiplication by a factor of four. Additionally, forming closely-spaced features entails use of high-resolution optical scanners, which can increase processing costs. For example, a 248 nanometer (nm) optical scanner with a resolution of about 100 nm costs about $20 million at the time of filing, and a 193 nm scanner with a resolution of about 65 nm costs about $30 million. Additionally, photoresist materials currently available for use with 193 nm scanners are less robust than those available for 248 nm scanners, adding to the limitations of spacer formation on state-of-the-art photoresist masks.
Accordingly, it would be advantageous to form features below the minimum pitch of a photolithographic technique, while minimizing the number of processing steps and, ultimately, processing times and costs. Additionally, it would be advantageous to permit flexibility in the degree to which pitch is multiplied.
It will be appreciated that the drawings and features therein are not drawn to scale.